Design and Analysis of Full Adders using Adiabatic Logic

Title: Design and Analysis of Full Adders using Adiabatic Logic
Publisher: Guru Nanak Publications
ISSN: 2278-0947
Series: Volume 3 Issue 1
Authors: Bhaskara Uma Mahesh


Abstract

In this paper comparison of adiabatic logic designs was made with objective to provide new low power solutions for very large scale integrations (VLSI) designers. Further, to limit the power dissipation alternative solutions are proposed. A new full adder was designed using ECRL and PFAL logics and simulations of the same were done using Microwind and DSCH. The analysis of the average dynamic power dissipation with respect to frequency and load capacitance was conducted and shown that amount of power dissipation. The circuit simulations shows adiabatic designs can save energy by considerable factor.

Keywords

Adiabatic Logic, CMOS, DSCH, ECRL, Full Adder, IC, NAND, PFAL, PMOS, ULSI, VLSI.

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